This invention relates generally to programmable devices such as field programmable gate arrays, and specifically to methods for selectively replacing microcontroller firmware code.
FIG. 1 shows a conventional Field Programmable Gate Array (FPGA) 1 having an array of configurable logic blocks (CLBs) 2 surrounded by input/output blocks (IOBs) 3. The CLBs 2 are individually programmable and can be configured to perform a variety of logic functions ranging from simple AND gates to more complex functions of a few input signals. A programmable interconnect structure 4 includes a matrix of programmable switches (PSMs) 5 which can be programmed to selectively route signals between the various CLBs 2 and IOBs 3 and thus produce more complex functions of many input signals. The IOBs 3 can be configured to drive output signals from the CLBs 2 to external pins (not shown) of FPGA 1 and/or to receive input signals from the external FPGA pins.
The CLBs 2, IOBs 3, and PSMs 5 of FPGA 1 are programmed by loading configuration data into memory cells (not shown for simplicity) connected to CLBs 2, IOBs 3, and PSMs 5. These memory cells control various switches and multiplexers within respective CLBs 2, IOBs 3, and PSMs 5 which implement logic and routing functions specified by the configuration data in the memory cells. Configuration data is provided to FPGA 1 via a configuration port 6 and thereafter routed to the memory cells using a dedicated configuration structure (not shown here but described in U.S. Pat. No. Re 34,363, 5,430,687, 5,742,531, and 5,844,829). Configuration port 6 is connected to the dedicated configuration structure by a configuration access port (CAP) 7, which is essentially a bus access point. Further information regarding various types of FPGAs can be found in xe2x80x9cThe Programmable Logic Data Book 1998xe2x80x9d, published in 1998 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
Configuration data is typically downloaded to an FPGA from a host system such as a personal computer or workstation using an FPGA interface cable, as illustrated in FIG. 2. Well known design tool software operating on a suitable microprocessor within host system 20 creates a configuration bitstream which embodies the logic functions desired to be implemented by the target FPGA. The configuration bitstream is downloaded from host system 20 to interface cable 15 using, for instance, a serial port or a USB port. The interface cable 15 preferably includes an on-board FPGA that customizes the configuration bitstream received from the host system 20 into a format usable by target FPGA 10, although in some embodiments host system 20""s microprocessor is used to customize the configuration bitstream for target FPGA 10. Since an FPGA is able to customize configuration data at a rate much faster than that of a microprocessor, FPGA interface cables having an on-board FPGA provide superior performance.
The default firmware code for the interface cable""s microcontroller is typically stored in a dedicated, non-volatile memory. Upon power-up of the interface cable, the microcontroller reads the firmware code from the dedicated memory, and then boots up using the default firmware code. If it becomes necessary to modify the firmware code, e.g., where a software bug is discovered in the default firmware, or perhaps where a newer version of the firmware code is available, the dedicated memory is typically re-programmed with the new firmware code. Then, the interface cable is reset, and the microcontroller boots up using the new firmware code read from the dedicated memory.
Updating the microcontroller""s firmware code in the manner described above is burdensome and time consuming. First, resetting the interface cable typically requires the user to manually activate a reset switch on the interface device, which is inconvenient and time consuming. Further, since the entire interface cable is reset in order to re-boot the microcontroller, the on-board FPGA must also be reset and then configured again, thereby undesirably consuming additional time. In addition, since the new firmware code is typically written to the same memory space that stores the default design, the default firmware code is no longer available after the firmware update. Accordingly, if a problem develops with the new firmware code, the default firmware code is not available, and thus must be re-programmed into the memory and the interface cable again reset.
The present invention provides a method for selectively overlaying portions of the default firmware code for a microcontroller of an FPGA interface device. In accordance with the present invention, an FPGA interface device includes a microcontroller, an on-board FPGA, and a memory having first and second pages. Upon initial power-up of the interface device, the default firmware code is loaded into the first memory page. Thereafter, the microcontroller executes instructions received from a host system using the firmware code loaded into the first memory page. Where it is desired to update or modify the firmware code, an overlay code is downloaded to the interface device and thereafter stored in the second memory page. The overlay code corresponds to selected portions of the default firmware code. Overlay flags are asserted for each of the selected portions of the default firmware code for which a corresponding overlay code is loaded in the second memory page. Then, during execution of subsequent instructions received from the host system, the overlay code is substituted for corresponding portions of the default firmware code for which the overlay flags are asserted. In this manner, the default firmware code may be selectively replaced by a new overlay code without resetting the interface device, thereby saving time. Further, by substituting the overlay code for selected portions of the default firmware code, as opposed to downloading an entirely new firmware code, the default firmware code is advantageously retained in the first memory page. Thus, for example, if the new overlay code is defective, the default firmware is easily reinstated by selectively de-asserting the overlay flags.